1. Field of the Invention
This disclosure relates to a MOS transistor, and more particularly, to a recessed gate transistor structure having a recess type gate, and a method of forming the same.
2. Description of the Related Art
Techniques of manufacturing semiconductor devices are being developed worldwide in response to the requirements of semiconductor users, and through the endeavors of semiconductor manufacturers. In addition, semiconductor manufacturers are developing enhanced high-speed, miniaturized, highly-integrated, and large-capacity semiconductor devices through more stabilized and smooth operations. Design rules for semiconductor devices are reduced in order to integrate more semiconductor devices in a semiconductor chip of limited size. These efforts reduce intervals between gates, potentially causing among other problems, a short or leakage current.
In order to solve the shortcomings it is well known in the art that a recessed gate type transistor with a gate insulation layer is formed in both the side wall and bottom face of a recess formed in a substrate. Then a conductive layer, such as polysilicon, is filled within the recess. This is in contrast to a planar gate type transistor having a gate electrode formed on a planar substrate.
A conventional recessed gate forming method is described as follows, referring to FIGS. 1 to 6.
FIG. 1 is a layout of a conventional recessed gate transistor. FIGS. 2 to 5 are cross-sectional views illustrating a method of forming a conventional recessed gate transistor. FIG. 6 is a cross-sectional view illustrating a misalignment generated while forming the conventional recessed gate transistor. FIGS. 2 to 6 illustrate a cross-sectional face along the line I–I′ in FIG. 1.
With reference to FIGS. 1 through 6, the layout of the conventional recessed gate transistor and the conventional method of forming recessed gate transistors will be described.
Referring first to FIG. 1, two substantially parallel patterned first-gate electrodes 101 are disposed perpendicular to a length direction of each active region 102. Each active region 102 is surrounded by a non-active region 104. Thus, several transistors are manufactured simultaneously. Second gate electrodes 100, formed in a recess only on the active regions 102, are disposed under the first gate electrodes 101. The first gate electrodes 101 are distanced substantially uniformly from each other and are disposed substantially parallel. However, if a misalignment is generated while forming the first gate electrode 101, the first gate electrode 101 disposed on the non-active region 104 contacts (106) a portion of an adjacent active region, causing a short, as shown in FIG. 1.
Referring to FIG. 2, a device isolation film 202 for defining the active region and the non-active region is formed in a determined region of a p- type semiconductor substrate 200, and a well region 204 is formed by ion implanting p- type impurities into the semiconductor substrate. Subsequently, a threshold voltage control region 206 is formed by ion implanting the p− type impurities into the active region defined by the device isolation film 202, then an impurity induction layer 208 is formed by ion implanting n- type impurity into the active region.
With reference to FIG. 3, a silicon nitride layer 209 and an oxide layer 211 are formed thereon, next a recess is formed at a portion of the active region through a photolithography process.
Referring to FIG. 4, a gate oxide layer 213 is formed within the recess, and then a polysilicon layer 210 is formed to fully fill into the recess with the gate oxide layer. Subsequently, a conductive layer 212 and a capping layer 214 are sequentially formed on the polysilicon layer 210.
With reference to FIG. 5, a gate stack is formed through a photolithography process. Then relatively low energy n- type impurity ions are implanted into the impurity induction layer 208 using the gate stack as an ion implantation mask, forming a low density n− type source/drain region. Next, a gate spacer 216 is formed in a sidewall of the gate stack, then relatively high energy impurity ions are implanted into the n− type source/drain region using the gate spacer as an ion implantation mask. Thus, a high density n+ type source/drain region is formed on a portion of the low density n− type source/drain region. Thereby, the conventional recessed gate transistor is obtained.
Referring to FIG. 6, the gate to be formed on an upper part of the non-active region actually contacts (218) with an upper part of the active region because of a misalignment, causing a short.
The conventional gates are formed on all the active and non-active regions. This may bring about a short effect between the gate conductive layer formed on the non-active region and the active region if there are misalignments while forming the gate. Also, in a subsequent process a short is generated between a self aligned contact (SAC) and the active region. The short is caused by the misalignment because an alignment margin can't be sufficiently ensured as design rules for semiconductor devices are gradually reduced.
Embodiments of the invention address these problems.